Bay claims that the key to the Montego processor's performance of guaranteed sustainable packet processing of 31.25 mpps (regardless of traffic patterns or networks services), whilst supporting data throughput of up to 16 Gbit/s, is its deterministic pipeline architecture, which Bay says is necessary to guarantee a line rate at minimum packet size.

Bay Microsystems commented that most 2.5 Gbit/s class network processors currently available on the market are based on parallel, multi-threaded RISC architectures, and are not deterministic and therefore cannot guarantee sustained line rate performance.

Bay added that Montego's programmable AnyMapping capability supports line rate transformation and forwarding of any legacy protocol such as SONET, ATM, Ethernet, IPv4 and Frame Relay, and any proprietary or emerging protocols such as MPLS and IPv6.

To support customer design efforts, Bay has also introduced a simulation and emulation design environment as well as a complete Java GUI-based system reference design called the Internetworking Development System. This not only provides a complete device level-programming tool, but also enables system emulation, simulation and debug.

Bay Microsystems was founded by:

1. Chairman Rick Bleszynski: founded Softcom Microsystems in 1996, and served as a member of the Board of Directors, as well as the VP of Engineering/CTO; described as responsible for architectural development of both the GigaBlade Broadband Accelerator and the SoftcomEngine - the world's first single-chip full-duplex OC-12c network processor. Intel acquired Softcom in July 1999.

2. President Ash Dhar: previously in executive management roles at Xilinx, S3, Global Village Communications, Rise Technology and Paradigm Technologies; before that 2+ years with Texas Instruments and 8 years with Intel in worldwide operations.

3. VP of Engineering Tony Chiang: VP of VLSI Design Engineering at C-Cube, and prior to that described as responsible for VLSI Design Engineering at Hitachi and AMD.

4. Director of Systems Engineering/Architecture Man Trinh: prior to Bay, principally involved with the architecture and implementation of the GigaBlade network accelerator product line for Softcom. Described as largely responsible for the implementation of Bay's innovative NPU architecture. Has been awarded several patents in the area of broadband networking.

5. SVP of Marketing/Sales Charles (Chuck) Gershman: prior to Bay was VP of Sales and Business Development at Softcom Microsystems.

NB: The $21 million funding was quoted by San Jose Mercury News January 27th 2002. $4 million seems to have been subscribed in early 2000 funding by Selby Venture Partners, Alliance Venture Partners and Needham Capital. $17 million seems to have been forthcoming in early 2001, in a round led by Thomas Weisel Venture Partners and also including first round investors. The company itself has not directly published a number.

It may be worth noting that the company's Board includes two of the five founders, Bleszynski and Dhar, plus representatives of the two major investors, Selby Venture Partners and Thomas Weisel Venture Partners, plus also Bernie Vonderschmitt, the Chairman of Xilinx Corp – this suggests that Xilinx may have some strategic investment in the company, which may not be in direct cash but in kind.

COMMENT AND ANALYSIS

The announcement by Bay Microsystems of the completion of the design of its 10 Gbit/s single chip network and traffic management processor appears to be a substantial achievement, beating from a relatively late start at least 20 competitors such as Intel (estimated to have around one third of current generation processor designs), AMCC, Motorola, Vitesse, Agere, IBM, Teradiant, Terago, Xelerated Packet Devices, Ezchip, ClearSpeed and several others.

The degree of competition and the narrowness of Bay Microsystems' advantage may be judged from the fact its announcement quotes Village Networks, a reference customer, as having looked at 10 possible suppliers. The implication has to be that a significant number, say 60%, of these suppliers must be claiming that they are close to releasing a comparable product, otherwise they would be unlikely to have been considered seriously by Village in the first place.

This degree of competitiveness, interestingly enough, has a correlative effect on decision making by customers, who are also under pressure to come to market quickly, because the wide availability of suppliers means that their own competitors also have lots of choice and they cannot afford to hang about. Certainly under normal usage, Bay Micro's "many" customers could not mean less than six to ten and possibly up to twice that, which looks like a fairly fast rate of takeoff.

NB: The human story behind the Bay Microsystems announcement was covered between the end of January and mid-March in a series of articles by the San Jose Mercury News, which mainly focused on the personal histories, total dedication and day to day interdependence over two years of the design team. The last SJMN report covered the receipt of the 16 prototype units of the latest complete design chip from Taiwan and the harrowing (100 pairs of crossed fingers) next day testing of the chip, in parallel with a commercial lab in Fremont, to confirm whether the chips were at least minimally functional or not.